Implementation of the Complete Predictor for DDR3 SDRAM

Dual DIMM DDR2 and DDR3 SDRAM Interface Design Guidelines

This application note describes guidelines for implementing dual unbuffered DIMM DDR2 and DDR3 SDRAM interfaces. This application note discusses the impact on signal integrity of the data signal with the following conditions in a dual-DIMM configuration: ■ Populating just one slot versus populating both slots ■ Populating slot 1 versus slot 2 when only one DIMM is used ■ On-die termination (ODT...

New SEE Test Results for 4 Gbit DDR3 SDRAM

New generation 4 Gbit DDR3 SDRAMs from Samsung and Elpida have been tested for hard errors and device SEFIs under heavy ions.

Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA

TN-41-13: DDR3 Point-to-Point Design Support

• TN-00-20: Understanding the Value of Signal Integrity Testing • TN-41-02: DDR3 ZQ Calibration • TN-41-04: Dynamic On-Die Termination • TN-46-02: Decoupling Capacitor Calculation for a DDR Memory Channel • TN-46-06: Termination for Point-to-Point Systems • TN-46-11: DDR SDRAM Point-to-Point Simulation Process • TN-46-14: Hardware Tips for Point-to-Point System Design: Termination, Layout, and ...

TN-41-02: DDR3 ZQ Calibration

Introduction For more robust system operation, the DDR3 SDRAM driver design has been enhanced with reduced capacitance, dynamic on-die termination (ODT), and a new calibration scheme. The capacitance reduction comes from the use of a new “merged” driver. With the new driver, circuitry that makes up the output driver is shared for use in ODT. Separate structures were used on DDR2 for the output ...